ADSL, How it Works
ADSL is something of mystery with regards to how a DSP chip which is essentially used as a high frequency "sound card" line trains or "syncs" with a line card in a CO (Central Office). This is how that works.
Basically the CO sends a set of tones which the CPE (Customer Premise Equipment "your DSL modem") detects and then proceeds to perform a line qualification, or training session.
A set of test tones is sent and used to determine suitability of various tones for reliably carrying data bits. These represent "buckets" into which the bits can be assigned during a tranmission. Part of the buckets are used for "Upstream" transfers, some of the buckets are used for "Downstream" transfers. The majority of the buckets are assigned to "Downstream" transfers and that is why the "A"DSL is "Assymmetric" or "lopsided" - it "favors" the downstream direction.
To actually prepare and transfer a sequence of bits or "byte" of information, the DSP chip assigns the individual bits to the available buckets for transfer (some of the buckets may be deprioritized, or "black listed" as predetermined by the line "training" session).
Then it performs a Fast Fourier Transform to convert the composite arrangement of bits into a continuous waveform. It essentially "smears them into an analog signal" and sends that signal. The assumption is that by transforming from the digital to the analog domain, or the "Frequency Domain" the signal will be more resistant to signal degradation or "damage" in the instaneous "Time Domain".. basically this means if there is a snap crackle or "pop" on the line. The transmission will likely make it "across" the line in some fashion which can be "error corrected" when its converted back from the "Frequency Domain" into the "Time Domain" and the individual bits are recovered from the designated buckets.
The CO equipment also has a "map" of the chosen frequency bins determined during the line training session with the CPE equipment, and this influences how it actually carries out the [Inverse Fast Fourier Transform].
Bit error correction is conducted by a combination of Reed Solomon and other methods, and the Near and Far indications are used to describe whether an error was corrected at the CPE receiving end or at the CO transmission end and vice versa.
CRC or "check sums" are used to verify the RS error correction actually worked, or failed in which case "Uncorrectable" errors are determined to have occurred and a "re-transmission" of the data is automatically requested.
Excessive uncorrectable or RS activity should automatically trigger a "line retraining" event, a "line drop" or a "re-sync event".. the purpose of which is to re-characterize the line and try to construct a "new algorithm" from the detected available Frequency Bins on a line. Some modems do not do this step well, or in co-ordination with the CO. Line "syncing" is not always successful and a complete failure can lead to an inability to "re-connect" event after a previously successful connection.
Typically during "training" the CO and CPE "agree" on a "sync rate" or how fast the Upstream and Downstream rates will be once the the "training" event is over and communications begins. Based on various chipset implementations the "sync" rate may be higher or lower, either as a result of or consequence of compatiblity in their sync procedures, and or various deviations from the established "Standards". For example one vendors chipset may choose to sync at a "faster" rate in Upstream or Downstream or both when it detects it is communicating with equipment made by the same vendor.. and yet choose to negotiate a slower (more stable) rate with equipment made by a different vendor.
End users on the other hand may want to attempt faster sync rates for various reasons, or have the ability to "override" the decisions of the chip makers. This has lead to a number of supported and unsupported "hacks" by end users seeking to monitor and influence the training session.
Unfortunately since there are few direct implementaions of "special functions" made available by chipset or modem vendors. This is something of an art, and something of a dying art at that as ADSL chips move further and further into history.